Previously, extensive physical tuning of the clock signal path length has been required to synchronize component operations in electronic devices. As electronic systems, such as computers have progressively become more complex, the timing requirement becomes extremely burdensome. Further, as systems have increased in speed, the need for more precise timing has manifested itself and created an additional burden on the designer. Even as a physically tuned system operates properly, the exchange or replacement of subsystems known as field replaceable units (FRUs) create tuning mismatches which cannot be readily overcome. Accordingly, in order to make FRUs replaceable and effective, it is necessary to physically tune all timing links to a very precise standard.
The same problem is exhibited whenever a chip or component is replaced in the process of repairing FRUs. Such mismatches may result in unreliability or performance degradation.
Alternatively, the system must be designed with sufficient skew budget to accommodate the anticipated misalignment and accommodate the increased jitter or misalignment. Such increased skew budget or allowance results in a corresponding decrease in operating speed of the system. An increase in the allowable skew of the timing signal is antithetical to the goal of increased system operating speed.
A digital phase aligning circuit and method is described in U.S. patent application Ser. No. 08/269,226, filed Jun. 30 1994, entitled Electronically Tunable Computer Clocking System and Method of Electronically Tuning Distribution Lines of a Computer System, by. Robert P. Masleid et al. While this circuit permits alignment of the phases of the clock signal with a reference pulse as received by the circuit, the control of the alignment of pulses at remote FRUs and chips still must be accounted for and controlled.